Anand Anil Pathak

Title: Anand Anil Pathak and Bias Scaling for N-Bit Hardware Acceleration.

Introduction

Anand Anil Pathak is an inventor based in Bengaluru, India. His patent work addresses efficient neural-network computation using constrained hardware.

Latest Patents

Pathak is associated with 1 patent, titled “Bias Scaling for N-Bit Constrained Hardware Acceleration.” The invention describes an integrated circuit with memory for weights and biases, an N-bit fixed-point matrix operations accelerator, and a processor. For each convolution layer, the processor adjusts feature and weight scales when the accumulator scale exceeds the maximum bias scale. It then rescales input features, quantizes weights and biases, and uses the accelerator to perform the convolution and generate output features. Those outputs become inputs to the next layer, while output feature ranges are fed back as the process continues through the network.

Career Highlights

Pathak works at Texas Instruments Corporation. His patent reflects work on coordinating quantization and scaling with fixed-point hardware constraints to support convolution operations.

Collaborations

Anshu Jain and Manu Mathew are identified as Pathak’s coworkers. The available information does not specify their roles in the patent.

Conclusion

Anand Anil Pathak’s patent focuses on scaling and quantization techniques that help convolution layers operate within the limits of N-bit hardware acceleration.