An-Chi Tsai

Title: An-Chi Tsai: Innovator in Pipelined Data Processing

Introduction

An-Chi Tsai is a notable inventor based in Hsinchu, Taiwan. She has made significant contributions to the field of data processing, particularly through her innovative patent that addresses computation errors in pipelined data systems. Her work exemplifies the intersection of technology and engineering, showcasing her expertise and dedication to advancing the field.

Latest Patents

An-Chi Tsai holds a patent titled "Variable-latency speculating pipelined booth multiplier with statistical carry estimation for error detection and recovery." This patent provides a method for processing pipelined data using a variable-latency speculating booth multiplier (VLSBM). The method includes a first operation that involves partitioning partial products into a least significant part (LSP) and a most significant part (MSP). It estimates a carry of the LSP, computes the MSP based on the estimated carry, and independently computes the LSP to obtain a true carry. The process also includes detecting computation errors by comparing the estimated carry with the true carry. The second operation corrects any computation errors based on the difference between the estimated carry and the true carry. This innovative approach enhances the reliability of pipelined data processing.

Career Highlights

An-Chi Tsai is affiliated with National Yang Ming Chiao Tung University, where she continues to contribute to research and development