Hollister, CA, United States of America

Amelia Clara Muro

This inventor holds 1 USPTO granted patent. Top assignee: Hitachi Global Storage Technologies Netherlands B.v.. Active years: 2007.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Amelia Clara Muro. Retrieved from https://idiyas.com/inventor/amelia-clara-muro

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile


Average Co-Inventor Count = 3.0

ph-index = 1

Forward Citations = 4(Granted Patents)


Company Filing History:


Years Active: 2007

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1 patent (USPTO):Explore Patents

Title: Amelia Clara Muro: Innovator in Wafer Processing Technology

Introduction

Amelia Clara Muro is a prominent inventor based in Hollister, California. She has made significant contributions to the field of wafer processing technology. Her innovative approach focuses on optimizing yield in batch processing tools, which is crucial for the semiconductor industry.

Latest Patents

Amelia holds a patent for her invention titled "Aggregated run-to-run process control for wafer yield optimization." This method enhances the processing of wafers in a batch processing tool by minimizing within-batch wafer variation. The technique is particularly beneficial when processing less than a full batch of wafers. By determining all possible wafer position combinations and selecting the one that results in the least variation, her method significantly improves yield.

Career Highlights

Amelia is currently employed at Hitachi Global Storage Technologies Netherlands B.V., where she applies her expertise in wafer processing. Her work has been instrumental in advancing the efficiency and effectiveness of semiconductor manufacturing processes.

Collaborations

Amelia has collaborated with notable colleagues, including Andrew Crehan Walker and Yeak-Chong Wong. Their combined efforts contribute to the innovative environment at Hitachi Global Storage Technologies.

Conclusion

Amelia Clara Muro is a trailblazer in wafer processing technology, with her patent reflecting her commitment to innovation and excellence in the field. Her contributions continue to shape the future of semiconductor manufacturing.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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