This inventor holds 2 USPTO granted patents. Top assignee: University of Rochester. Active years: 2004.
Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile
Company Filing History:
Years Active: 2004
Title: Alper Buyuktosnoglu: Innovator in Memory Hierarchy Design
Introduction
Alper Buyuktosnoglu is a prominent inventor based in Rochester, NY (US). He has made significant contributions to the field of processor architecture, particularly in memory hierarchy design. With a total of 2 patents, his work focuses on enhancing energy efficiency and performance in general-purpose processors.
Latest Patents
Alper's latest patents include innovative designs aimed at improving memory hierarchy performance. The first patent, titled "Memory hierarchy reconfiguration for energy and performance in general-purpose processor architectures," introduces a cache and TLB layout that utilizes repeater insertion. This design provides dynamic low-cost configurability, allowing for a trade-off between size and speed based on application phase. A configuration management algorithm is also included, which dynamically detects phase changes and responds to an application's hit and miss intolerance, ultimately enhancing memory hierarchy performance while considering energy consumption.
The second patent, "Dynamic reconfigurable memory hierarchy," shares similar principles. It also leverages repeater insertion for cache and TLB layout, offering dynamic configurability. The configuration management algorithm in this patent similarly detects phase changes and reacts to application demands, ensuring optimal performance and energy efficiency.
Career Highlights
Alper Buyuktosnoglu is affiliated with the University of Rochester, where he continues to advance research in processor architecture. His work has garnered attention for its practical applications in improving computing efficiency.
Collaborations
Alper collaborates with esteemed colleagues such as Sandhya Dwarkadas and Rajeev Balasubramonian. Their combined expertise contributes to innovative research and development in the field.
Conclusion
Alper Buyuktosnoglu is a key figure in the advancement of memory hierarchy design, with patents that significantly enhance processor performance and energy efficiency. His contributions are vital to the ongoing evolution of computing technology.
Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile