Ajay Kumar Rathee

Title: Ajay Kumar Rathee and Processor-Based Innovation

Introduction

Ajay Kumar Rathee is an inventor based in San Jose, California, and works at Qualcomm Incorporated. His patent work includes processor-based technology designed to improve instruction translation lookaside buffer (TLB) prefetching. He is associated with 2 patents.

Latest Patents

Rathee’s latest listed patent is “Using Retired Pages History for Instruction Translation Lookaside Buffer (TLB) Prefetching in Processor-Based Devices.” The invention describes a history-based instruction TLB prefetcher circuit that tracks retired instruction pages. When the circuit detects that a retired instruction belongs to a page with a virtual address different from the last recorded retired-page address, it updates the indicator with the new address. This history can support TLB prefetching in processor-based devices.

Career Highlights

Rathee’s patent activity reflects work on processor architecture and memory-translation performance. His disclosed invention focuses on using information about recently retired pages to guide instruction TLB prefetching.

Collaborations

Rathee works at Qualcomm Incorporated and is associated with coworker Conrado Blasco. The provided information does not specify their roles or the nature of their collaboration.

Conclusion

Ajay Kumar Rathee’s patent work at Qualcomm centers on using retired-page history to inform instruction TLB prefetching, contributing to innovation in processor-based devices.