IDiyas

For the Inventor, By the Inventor

San Jose, CA, United States of America

Ajay Dalvi

USPTO Granted Patents = 4

Average Co-Inventor Count = 1.5

ph-index = 3

Forward Citations = 20(Granted Patents)


Location History:

  • San Francisco, CA (US) (2007 - 2008)
  • San Jose, CA (US) (2006 - 2012)

Company Filing History:

goldMedal4 out of 5,002 
 
Xilinx, Inc.
 patents

Years Active: 2006-2012

where 'Filed Patents' based on already Granted Patents

4 patents (USPTO):
1. 8121240 - Statistical measurement of average edge-jitter placement on a clock signal (2012-02-21),
2. 7370245 - Cross-correlation of delay line characteristics (2008-05-06),
3. 7305604 - Determining edge relationship between clock signals (2007-12-04),
4. 7138829 - Measuring input setup and hold time using an input-output block having a variable delay line (2006-11-21),
This text is generated by artificial intelligence and may not be accurate.
Please report any incorrect information to support@idiyas.com
Loading…