Singapore, Singapore

Adarsh Bhat

This inventor holds 1 USPTO granted patent. Top assignee: Rockwell Automation Technologies Incorporated. Active years: 2019.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Adarsh Bhat. Retrieved from https://idiyas.com/inventor/adarsh-bhat-qobuy8kb

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile


% Patents Active = 100.0

Average Co-Inventor Count = 5.0

ph-index = 1

Forward Citations = 1(Granted Patents)


Company Filing History:


Years Active: 2019

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1 patent (USPTO):Explore Patents

Title: Adarsh Bhat: Innovator in Ladder Logic Programming

Introduction

Adarsh Bhat is a notable inventor based in Singapore, SG. He has made significant contributions to the field of programming, particularly in ladder logic systems. His innovative approach has led to the development of a unique patent that enhances programming efficiency.

Latest Patents

Adarsh holds a patent for "Ladder logic graphical programming and textual programming synchronization." This invention involves a processor that dynamically synchronizes a graphical ladder logic programming interface with an executable code base of ladder logic instructions. Additionally, the processor concurrently synchronizes a textual ladder logic programming interface to the executable code base. This advancement streamlines the programming process and improves overall functionality.

Career Highlights

Adarsh Bhat is currently employed at Rockwell Automation Technologies Incorporated, where he applies his expertise in programming and automation technologies. His work focuses on enhancing the efficiency and effectiveness of programming systems, making significant strides in the industry.

Collaborations

Adarsh has collaborated with talented individuals such as Jean-Sebastien Kovacs and Haojie Zheng. These partnerships have fostered innovation and contributed to the development of advanced programming solutions.

Conclusion

Adarsh Bhat's contributions to ladder logic programming demonstrate his commitment to innovation and excellence in the field. His patent and collaborative efforts reflect a dedication to advancing technology and improving programming practices.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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