Abhishek Shrikant Agarwal

Title: Abhishek Shrikant Agarwal: Semiconductor Packaging Inventor

Introduction

Abhishek Shrikant Agarwal is an inventor based in Gilbert, Arizona, whose work includes semiconductor packaging technology. He is associated with Qualcomm Incorporated and is named on 1 patent.

Latest Patents

Agarwal’s patent, “Integrated Circuit Package Having a Substrate Employing Reduced Area, Added Metal Pad(s) to Metal Interconnect(s) to Reduce a Die to a Substrate Clearance and Related Fabrication Methods,” describes a design intended to reduce the height of an integrated circuit package.

The invention uses additional metal pads with a smaller cross-sectional area than the underlying pads. These smaller pads connect to die interconnects through solder joints, while the substrate’s metal interconnects provide support and signal-routing paths. During soldering, the solder flows along the reduced-area pads, enabling a smaller clearance between the die and substrate.

Career Highlights

Agarwal’s disclosed work addresses a practical challenge in integrated circuit packaging: reducing package height while maintaining electrical connections and structural support. His patent identifies a substrate and pad configuration designed to achieve that reduction.

Collaborations

Agarwal’s listed coworkers include Ashish Alawani and Heun Gun Shin. His patent is associated with Qualcomm Incorporated.

Conclusion

Abhishek Shrikant Agarwal’s patent focuses on a compact integrated circuit package, using reduced-area metal pads and solder connections to decrease the clearance between a die and its substrate.