Sikandrabad, India

Abhishek Jain

This inventor holds 1 USPTO granted patent. Top assignee: Nxp B.v.. Active years: 2026.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Abhishek Jain. Retrieved from https://idiyas.com/inventor/abhishek-jain-95di6i44

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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Average Co-Inventor Count = 1.0


Company Filing History:


Years Active: 2026

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1 patent (USPTO):Explore Patents

Title: Abhishek Jain: Inventor in Sikandrabad

Introduction

Abhishek Jain is an inventor based in Sikandrabad, India. His patent work includes a design for optimizing broadcast operations in a multicore processing system with a distributed cache. He is associated with NXP B.V. and has 1 patent.

Latest Patents

Jain’s patent, “Optimization of Broadcast Operations in Multiple Core Processing System with a Distributed Cache,” describes a multicore system with multiple first-level (L1) caches and a distributed second-level (L2) cache divided into uniquely identified partitions. A routing network enables communication between the L1 and L2 caches.

When an L1 cache’s request to an L2 partition is rejected because the partition is busy, the L1 cache waits for a retry message containing the relevant partition identifier before resending the request. The identifier can be determined by the L1 cache when it sends the request, or included by the L2 partition in its rejection message. This approach coordinates retries and helps optimize broadcast operations.

Career Highlights

Jain’s listed patent focuses on cache communication and request handling in multicore processing systems. His work is associated with NXP B.V., a company known for developing semiconductor technologies.

Collaborations

Ayush Mishra is identified as Jain’s coworker. The available information does not specify their roles or describe a particular joint project.

Conclusion

Abhishek Jain’s patent addresses the coordination of cache requests and retries in multicore systems, highlighting his contribution to processor and cache-system design.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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