Bengaluru, India

Abdul M J Muthalif

This inventor holds 1 USPTO granted patent. Top assignee: Texas Instruments Corporation. Active years: 2006.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Abdul M J Muthalif. Retrieved from https://idiyas.com/inventor/abdul-m-j-muthalif

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile


% Patents Active = 100.0

Average Co-Inventor Count = 3.0

ph-index = 1

Forward Citations = 9(Granted Patents)


Company Filing History:


Years Active: 2006

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1 patent (USPTO):Explore Patents

Title: Abdul M. J. Muthalif: Memory-Array Timing Innovation

Introduction

Abdul M. J. Muthalif is an inventor based in Bengaluru, India, associated with Texas Instruments Corporation. His patent work addresses the challenge of sensing memory-array outputs when their delays vary.

Latest Patents

Muthalif is credited with 1 patent, titled “Determining Optimal Time Instances to Sense the Output of a Memory Array Which Can Generate Data Outputs with Variable Delay.” The invention describes a tracking circuit that generates sense-enable signals at suitable times. Its scalable driver block uses dummy cells with drive strengths matching cells in the memory array, approximating the delay produced by a column of memory cells. For smaller arrays, inverse control logic emulates the delay. The circuit uses a pulse from either the scalable driver block or the inverse control logic to trigger a sensing operation.

Career Highlights

Muthalif’s listed patent reflects work on memory circuitry and timing control. The approach is designed to help coordinate sensing with variable output delays in a memory array.

Collaborations

His listed coworkers include Nisha Padattil Kuliyampattil and Krishnan Santhana Rengarajan. The available information identifies them as coworkers but does not specify their roles in the patent.

Conclusion

Abdul M. J. Muthalif’s patent describes a tracking-circuit approach for timing memory-array sensing, using scalable drivers and inverse control logic to account for variable delays.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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