For the Inventor, By the Inventor

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Westborough, MA, United States of America

Tilera Corporation

USPTO Granted Patents = 69

% Expired Patents = 7.2

EPO Patents = 1

Trademarks = 1

Forward Citations = 2,704

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28 inventors (with patents filed for the assignee):

Anant Agarwal (37 out of 75 patents)

David M Wentzlaff (27 out of 37 patents)

Matthew Mattina (22 out of 64 patents)

4. Ian Rudolf Bratt (19 out of 38 patents)

5. Carl Ramey (11 out of 64 patents)

6. Richard Schooler (7 out of 17 patents)

7. Christopher D Metcalf (7 out of 17 patents)

8. Kenneth M Steele (7 out of 8 patents)

9. Liewei Bao (6 out of 14 patents)

10. Walter Lee (6 out of 9 patents)

11. Vineet Soni (6 out of 6 patents)

12. Patrick Robert Griffin (5 out of 12 patents)

13. Robert A Gottlieb (5 out of 11 patents)

14. Mathew Hostetter (4 out of 5 patents)

15. Chyi-Chang Miao (3 out of 13 patents)

Core Competencies:

Cache Management

Parallel Processing

Mesh Networks

Memory Access

Routing

Data Flows

Multicore Architectures

Pattern Matching

Dynamic Routing

Load Balancing

Flow Control

I/O Interfaces

69 patents: Sort by Forward Citations

1. 11151033 - Cache coherency in multiprocessor system (2021-10-19),

2. 9514050 - Caching in multicore and multiprocessor architectures (2016-12-06),

3. 9384165 - Configuring routing in mesh networks (2016-07-05),

4. 9329798 - Flow control in a parallel processing environment (2016-05-03),

5. 9298618 - Managing cache memory in a parallel processing environment (2016-03-29),

6. 9135215 - Route prediction in packet switched networks (2015-09-15),

7. 9063825 - Memory controller load balancing with configurable striping domains (2015-06-23),

8. 9009660 - Programming in a multiprocessor environment (2015-04-14),

9. 8949806 - Compiling code for parallel processing architectures based on control flow (2015-02-03),

10. 8934347 - Low latency dynamic route selection (2015-01-13),

11. 8886899 - Managing memory requests based on priority (2014-11-11),

12. 8799914 - Managing shared resource in an operating system by distributing reference to object and setting protection levels (2014-08-05),

13. 8799624 - Configurable device interfaces (2014-08-05),

14. 8738860 - Computing in parallel processing environments (2014-05-27),

15. 8737392 - Configuring routing in mesh networks (2014-05-27),

Company Overview

Tilera Corporation, based in Westborough, MA, specializes in advanced parallel processing technologies. The company focuses on developing multicore architectures that enhance performance across various applications. Key areas of expertise include cache management, memory access, and efficient data flow routing, which are essential for optimizing processing capabilities in complex computing environments. Tilera's innovations support a range of industries by enabling scalable and high-performance solutions in mesh networks and pattern matching.

Profile summary synthesized from public USPTO records and patent filings.

Company Badge

USPTO Data Jan 1 1976 - Oct 20 2026

69 Patents

#6 in Westborough, MA

#296 in Massachusetts

#5,317 in US

#10,773 in the World

Westborough, MA, United States of America

Tilera Corporation

Forward Citations = 2,704

28 inventors:

Anant Agarwal (37 out of 75 patents)

David M Wentzlaff (27 out of 37 patents)

Matthew Mattina (22 out of 64 patents)

4. Ian Rudolf Bratt (19 out of 38 patents)

5. Carl Ramey (11 out of 64 patents)

IDiyas Innovation Intelligence. (2026). Company Patent Portfolio: Tilera Corporation. Retrieved from https://idiyas.com/company/tilera

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]

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