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For the Inventor, By the Inventor

San Jose, CA, United States of America

Tality, L.p.


USPTO Granted Patents = 3

% Expired Patents = 33.3

Forward Citations = 30

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2 inventors (with patents filed for the assignee):

goldMedal Luverne Ray Peterson (2 out of 22 patents)

silverMedal LuVerne R Peterson (1 out of 12 patents)


3 patents:

1. 6385070 - Content Addressable Memory array, cell, and method using 5-transistor compare circuit and avoiding crowbar current (2002-05-07),
2. 6381162 - Circuitry and method for controlling current surge on rails of parallel-pulldown-match-detect-type content addressable memory arrays (2002-04-30),
3. 6331942 - Content addressable memory cell and design methodology utilizing grounding circuitry (2001-12-18),
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USPTO Data Jan 1 1976 - Oct 13 2026

3 Patents

#977 in San Jose, CA

#16,858 in California

#73,860 in US

San Jose, CA (US)
San Jose, CA, United States of America

Tality, L.p.

Forward Citations = 30

2 inventors:

goldMedal Luverne Ray Peterson (2 out of 22 patents)

silverMedal LuVerne R Peterson (1 out of 12 patents)

IDiyas Innovation Intelligence. (2026). Company Patent Portfolio: Tality, L.p.. Retrieved from https://idiyas.com/company/tality

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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