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San Jose, CA, United States of America

Ceremorphic, Inc.

Calculating rank

USPTO Granted Patents = 83

Trademarks = 1

Forward Citations = 25

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47 inventors (with patents filed for the assignee):

Venkat Mattela (32 out of 60 patents)

Wei Xiong (20 out of 34 patents)

Ryan P Boesch (18 out of 25 patents)

4. Martin Kraemer (18 out of 18 patents)

5. Sanghamitra Debroy (17 out of 19 patents)

6. Heonchul Park (17 out of 38 patents)

7. Akshaykumar Salimath (14 out of 15 patents)

8. Govardhan Mattela (11 out of 14 patents)

9. Suyash Kandele (9 out of 9 patents)

10. Joydeep Kumar Devnath (9 out of 9 patents)

11. Robert F Wiser (8 out of 9 patents)

12. Mohammed Sumair (7 out of 7 patents)

13. Ananya Shrivastava (7 out of 7 patents)

14. Lizy Kurian John (6 out of 22 patents)

15. Dylan Finch (6 out of 6 patents)

Core Competencies:

Chiplet Communication

Secure Encryption

Neural Networks

Fault Recovery

Memory Devices

Analog Multiplier

Skyrmion Logic

Multi-Threaded Processors

Blockchain Authentication

Power Saving Techniques

Asynchronous Memory

Data Access Management

83 patents: Sort by Forward Citations

1. 12776355 - System and method for spin orbit torque based memory device (2026-10-27),

2. 12748619 - System and method for opportunistic thread-switching for faster task-switching for handling interrupts and subroutines (2026-09-29),

3. 12699650 - Process for generation of addresses in multi-level data access (2026-08-04),

4. 12665862 - System and method for a multi-layer switching network (2026-06-23),

5. 12652051 - System and method for nanomagnet based logic device (2026-06-09),

6. 12613960 - Network based side channel attack (SCA) detection (2026-04-28),

7. 12587377 - Look up table (LUT) based encryption with tag-based verification (2026-03-24),

8. 12517781 - Storage of delay-logic values for enhanced fault recovery for dual processor lock step computing systems (2026-01-06),

9. 12462150 - Modular analog multiplier-accumulator unit element for multi-layer neural networks (2025-11-04),

10. 12430100 - Analog multiplier accumulator with unit element gain balancing (2025-09-30),

11. 12423957 - Systems and methods for a lightweight pattern-aware generative adversarial network (2025-09-23),

12. 12362911 - PRNG-based chiplet-to-chiplet secure communication using chaining of message blocks (2025-07-15),

13. 12361996 - System and method for spin orbit torque based memory device (2025-07-15),

14. 12308330 - Chip to chip interconnect beyond sealring boundary (2025-05-20),

15. 12300411 - System and method for nanomagnet based adder circuit (2025-05-13),

Company Overview

Ceremorphic, Inc., based in San Jose, CA, specializes in advanced secure communication technologies. The company focuses on developing innovative solutions that integrate chiplet communication, secure encryption, and neural networks to enhance data security and processing efficiency. Their research encompasses fault recovery mechanisms, memory devices, and analog multipliers, alongside pioneering work in skyrmion logic and multi-threaded processors. Ceremorphic aims to redefine the landscape of secure computing through cutting-edge technology and robust design principles.

Profile summary synthesized from public USPTO records and patent filings.

Company Badge

USPTO Data Jan 1 1976 - Nov 10 2026

83 Patents

#130 in San Jose, CA

#1,040 in California

#4,482 in US

#9,164 in the World

San Jose, CA, United States of America

Ceremorphic, Inc.

Forward Citations = 25

47 inventors:

Venkat Mattela (32 out of 60 patents)

Wei Xiong (20 out of 34 patents)

Ryan P Boesch (18 out of 25 patents)

4. Martin Kraemer (18 out of 18 patents)

5. Sanghamitra Debroy (17 out of 19 patents)

IDiyas Innovation Intelligence. (2026). Company Patent Portfolio: Ceremorphic, Inc.. Retrieved from https://idiyas.com/company/ceremorphic

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]

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