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For the Inventor, By the Inventor

Capitola, CA, United States of America

Ascenium Corporation


USPTO Granted Patents = 8

Forward Citations = 19

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3 inventors (with patents filed for the assignee):

goldMedal Peter Foley (7 out of 7 patents)

silverMedal Robert Keith Mykland (1 out of 11 patents)

bronzeMedal Ionut Hristodorescu (1 out of 8 patents)


8 patents:

1. 12748638 - Parallel processing architecture for branch path suppression (2026-09-29),
2. 12743377 - Parallel processing architecture with block move support (2026-09-22),
3. 12730668 - Load latency amelioration using bunch buffers (2026-09-08),
4. 12705092 - Highly parallel processing architecture with out-of-order resolution (2026-08-11),
5. 12578991 - Parallel processing architecture with distributed register files (2026-03-17),
6. 12504958 - Compute element processing using control word templates (2025-12-23),
7. 12493554 - Parallel processing using hazard detection and mitigation (2025-12-09),
8. 7840777 - Method and apparatus for directing a computational array to execute a plurality of successive computational array instructions at runtime (2010-11-23),
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USPTO Data Jan 1 1976 - Oct 13 2026

8 Patents

#3 in Capitola, CA

#8,540 in California

#35,924 in US

Capitola, CA (US)
Capitola, CA, United States of America

Ascenium Corporation

Forward Citations = 19

3 inventors:

goldMedal Peter Foley (7 out of 7 patents)

silverMedal Robert Keith Mykland (1 out of 11 patents)

bronzeMedal Ionut Hristodorescu (1 out of 8 patents)

IDiyas Innovation Intelligence. (2026). Company Patent Portfolio: Ascenium Corporation. Retrieved from https://idiyas.com/company/ascenium

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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