For the Inventor, By the Inventor

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Hsinchu, Taiwan

Andes Technology Corporation

USPTO Granted Patents = 33

Trademarks = 1

Forward Citations = 119

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27 inventors (with patents filed for the assignee):

Chuan-Hua Chang (9 out of 9 patents)

Hong-Men Su (8 out of 8 patents)

Thang M Tran (7 out of 168 patents)

4. Chi-Chang Lai (6 out of 9 patents)

5. Zhong-Ho Chen (5 out of 5 patents)

6. Chieh-Jen Cheng (3 out of 3 patents)

7. Wei-Hao Chiao (3 out of 4 patents)

8. Kun-Ho Liu (2 out of 2 patents)

9. I-Cheng Kevin Chen (2 out of 2 patents)

10. Jen-Chih Tseng (2 out of 4 patents)

11. Chun-Chang Yu (2 out of 2 patents)

12. Haw-Luen Tsai (2 out of 2 patents)

13. Li-Hung Chang (2 out of 2 patents)

14. Hsin-Ming Chen (1 out of 74 patents)

15. Yi-Jong Yeh (1 out of 1 patent)

Core Competencies:

Processor

Microprocessor

Cache Management

Memory System

Instruction Execution

Data Processing

Latency Shifting

Instruction Translation

Power Scaling

Pipeline Control

Software-Hardware Authentication

Interrupt Controller

33 patents: Sort by Forward Citations

1. 12769547 - Vector processing circuit and vector processing method with reused calculation circuit (2026-10-20),

2. 12572457 - Processor suitable for multi-segment accessing memory and operation method thereof (2026-03-10),

3. 12147810 - Processor, operation method, and load-store device for implementation of accessing vector strided memory (2024-11-19),

4. 12007902 - Configurable memory system and memory managing method thereof (2024-06-11),

5. 11797442 - Integrated circuit and method for executing cache management operation (2023-10-24),

6. 11687347 - Microprocessor and method for speculatively issuing load/store instruction with non-deterministic access time using scoreboard (2023-06-27),

7. 11467841 - Microprocessor with shared functional unit for executing multi-type instructions (2022-10-11),

8. 11281586 - Processor and way prediction method thereof (2022-03-22),

9. 11263013 - Processor having read shifter and controlling method using the same (2022-03-01),

10. 11204770 - Microprocessor having self-resetting register scoreboard (2021-12-21),

11. 11188478 - Apparatus and method for using instruction translation look-aside buffers in the branch target buffer (2021-11-30),

12. 11188468 - Processor and way prediction method thereof (2021-11-30),

13. 11163582 - Microprocessor with pipeline control for executing of instruction at a preset future time (2021-11-02),

14. 11132199 - Processor having latency shifter and controlling method using the same (2021-09-28),

15. 10579522 - Method and device for accessing a cache memory (2020-03-03),

Company Overview

Andes Technology Corporation, headquartered in Hsinchu, Taiwan, specializes in the design and development of RISC-V processor cores and related technologies. The company focuses on providing high-performance, low-power solutions for a variety of applications, including embedded systems, IoT devices, and automotive technologies. With a commitment to innovation, Andes Technology plays a significant role in advancing the RISC-V ecosystem, enabling developers to create efficient and scalable computing solutions across diverse industries.

Profile summary synthesized from public USPTO records and patent filings.

Company Badge

USPTO Data Jan 1 1976 - Oct 20 2026

33 Patents

#125 in Hsinchu

#551 in Taiwan

#20,162 in the World

Hsinchu, Taiwan

Andes Technology Corporation

Forward Citations = 119

27 inventors:

Chuan-Hua Chang (9 out of 9 patents)

Hong-Men Su (8 out of 8 patents)

Thang M Tran (7 out of 168 patents)

4. Chi-Chang Lai (6 out of 9 patents)

5. Zhong-Ho Chen (5 out of 5 patents)

IDiyas Innovation Intelligence. (2026). Company Patent Portfolio: Andes Technology Corporation. Retrieved from https://idiyas.com/company/andes-technology

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]

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