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Palo Alto, CA, United States of America

Advanced Semiconductor Assembly Technology

USPTO Granted Patents = 2

Forward Citations = 470

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1 inventor (with patents filed for the assignee):

Marcos Karnezos (2 out of 9 patents)

2 patents: Sort by Forward Citations

1. 5409865 - Process for assembling a TAB grid array package for an integrated circuit (1995-04-25),

2. 5397921 - Tab grid array (1995-03-14),

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USPTO Data Jan 1 1976 - Jan 6 2026

2 Patents

#548 in Palo Alto, CA

#20,566 in California

#92,696 in US

Palo Alto, CA, United States of America

Advanced Semiconductor Assembly Technology

Forward Citations = 470

1 inventor:

Marcos Karnezos (2 out of 9 patents)

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