Clara Courtaigne is a French designer with a wide range of skills, from creating objects and accessories to graphic design and illustration.
After working for several years at Chanel in the watch design studio, then at Bonpoint as an accessories stylist, she decided to launch her own projects in collaboration with companies from a variety of backgrounds, such as Bell & Ross, Carton Chic, Chanel joaillerie and Christofle. Her guiding principle is to pay particular attention to the quality of the objects she designs, to strive for rigour and simplicity, and to express a certain “joie de vivre”!
Since 2017, she has been the co-founder, with her sister, Juliette de Maupeou of the publishing house Siblings, which designs and manufactures tableware for contemporary tribes.
Clara is a graduate of Central Saint Martins College in London.
Patent №: D1060349 – Head-mounted display.
Patent №: D1060348 – Band.
Patent №: D1060347 – Head-mounted display.
Patent №: D1060346 – Head-mounted display.
Patent №: D1060345 – Band.
Patent №: D1060233 – Charging module.
Patent №: D1060224 – Charging module.
Turbine Technical Lead – Advanced Engines at Rolls-Royce North America.
Patent №: 12215593 – Turbine shroud assembly with inter-segment damping.
This disclosure relates to a turbine shroud assembly with first and second shroud segments and a seal assembly. The first shroud segment includes a carrier and a blade track segment, while the second is circumferentially adjacent. The seal assembly prevents gas leakage between them.
Semiconductor Packaging and Systems Integration Research – Principal Engineer at Intel Corporation.
Highly experienced Technologist consistently involved in the research of cutting-edge semiconductor packaging technologies and architectures delivering these to the development stage demonstrating vision, technical and project leadership and success.
Patent №: 12218069 – Multi-chip package with high density interconnects. This disclosure relates to an apparatus with first and second conductive contacts on a substrate, each with different pitch spacing. Conductive interconnects within the substrate couple corresponding contact groupings between die sites, with interconnects for different groupings arranged in separate substrate layers.
Founder and CTO at QROMIS, Inc.
Patent №: 12217957 – Engineered substrate structures for power and RF applications.
This disclosure relates to a substrate with a polycrystalline ceramic core encapsulated by adhesion and barrier layers. A conductive layer is coupled to the structure, along with a bonding layer, a single-crystal silicon layer, and an epitaxial semiconductor layer.
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