Distinguished Member Technical Staff; Message Oriented Middleware & Integration SME.
Patent №: 12223369 – Message oriented middleware cluster synchronization.
This method collects system parameters from multiple message-oriented-middleware (MOM) clusters, analyzes them with machine learning to predict anomalies, and shares relevant message metadata between clusters to support messaging operations.
Patent №: 12223360 – Testing framework with load forecasting. This method involves collecting and analyzing data on system components, focusing on their protocols and interfaces. Based on this analysis, component operations are tested, and their statuses are outputted based on the test results.
Distinguished Engineer at Nvidia.
Patent №: 12224941 – Method and apparatus for flexible and efficient analytics in a network switch.
This invention relates to a centralized network analytic device that uses shared on-chip memory for flexible counting, traffic monitoring, and flow sampling, all managed through software. In some cases, the device functions as a network switch.
HW Verification Engineer – FPGA/ASIC at Ericsson AB.
Patent №: 12225574 – Priority-dependent uci resource determination.
This invention provides systems and methods for priority-dependent Uplink Control Information (UCI) resource determination. A wireless device identifies UCIs to multiplex on a PUSCH, determines their priorities, calculates beta offset values, adjusts the UCI code rate, and transmits the UCI.
Mr. Onuki received the B.S. and M.S. degrees from University of Tsukuba, Tsukuba, Japan, in 2008 and 2010, respectively.
He joined Semiconductor Energy Laboratory Co., Ltd., Atsugi, Japan, in 2010, where he has been working on the development of LSI circuits and memories.
Patent №: 12225705 – Memory device having error detection function, semiconductor device, and electronic device. This memory device features error detection and high data density. It uses transistors on a semiconductor substrate for the driver circuit and thin-film transistors (TFTs) for memory cells. Stacking multiple TFT layers increases storage capacity, with the error detection circuit also formed using TFTs.
Patent №: 12223904 – Semiconductor device and method for driving semiconductor device. This invention relates to a semiconductor device and its driving method. The device includes first and second transistors, five switches, three capacitors, and a display element. The transistors’ gates, sources, and back gates are interconnected through switches and capacitors to control the display element efficiently.
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