Centurion+ Patent Holders as of June 11, 2024

Patent №: 11996095  – Augmented reality enabled command management. The exemplary embodiments disclose a method, computer program, and system for managing user commands. It involves collecting user commands to devices, extracting features from the data, and determining which commands should be executed on which devices based on the extracted features and models.

Ahmed received the IEEE Transactions on Communications Exemplary Reviewer in 2015, 2016, and 2017, and the IEEE Communications Letters in 2016.

He currently serves as an Editor for the IEEE Communications Letters, the IEEE Open Journal of the Communications Society, Physical Communications, and the Transactions on Emerging Technologies in Telecommunications. Shafie served as a Guest Editor for the IEEE Transactions on Cognitive Communications and Networking.

Patent №: 12010687 (June 11, 2024) – Techniques for enhanced sidelink feedback transmission.

A first wireless device receives a control message indicating a feedback resource configuration for transmitting feedback over a sidelink feedback channel with two or more symbol periods. The configuration may include start and length indicator values (SLIVs) and/or bitmaps. After receiving a sidelink message from a second wireless device, the first device transmits feedback based on the decoded message, using the configured symbol periods on the sidelink feedback channel.

Dr. Venkataraman received a Ph.D. in materials science and engineering from the University of Minnesota in Minneapolis, MN and a bachelor of technology degree in metallurgical engineering from the Indian Institute of Technology.

Patent №: 12009228 (June 11, 2024) – Low temperature chuck for plasma processing systems. A wafer chuck assembly includes a puck, shaft, and base. The puck has an electrically insulating top surface with embedded electrodes, an inner element with heat exchange channels, and an electrically conductive plate. The shaft features an electrically conductive housing connected to the plate and various connectors for the electrodes. The base has a conductive housing connected to the shaft housing and an insulating terminal block through which the connectors pass.

Patent №: 12009040 (June 11, 2024) – Detection of an incorrectly located read voltage. A memory device programs memory cells to store multiple bits per cell. After determining read voltages, it reads the cells using these voltages. For each page, the device counts cells with threshold voltages higher than the highest read voltage and compares this count to a predetermined range to evaluate the read voltages’ accuracy.

Patent №: 12009034 (June 11, 2024) – Classification of error rate of data retrieved from memory cells. A memory sub-system is configured to measure signal and noise characteristics of memory cells, determine optimized read voltages, generate features including compound features, classify the bit error rate, and control reading operations based on this classification.

Patent №: 12008719 (June 11, 2024) – Wide area augmented reality location-based services. Apparatus, methods, and systems for providing AR content involve obtaining an initial map, identifying views of interest, acquiring related AR content objects, creating experience clusters, and generating a tessellated tile map. A user device can then retrieve and display AR content based on location or recognition.

He also chairs the steering committee that directs etch concept and feasibility development. A recent focus is the implementation of atomic layer etching in critical applications and “etch aware” computational patterning.

He holds a BS in Chemical Engineering from the Indian Institute of Technology and a PhD in Chemical Engineering from the University of Houston, USA. There, his work contributed to developing the first ballistic electron beam-based plasma etchers, now in wide commercial use.

Prior to joining Tokyo Electron, Dr. Ranjan held technology leadership roles at Intel and Applied Materials. In both positions, he deployed new process and chamber technologies for leading-node pilot line development. Dr. Ranjan serves on numerous industry committees including the AVS Program Committee and ALE workshop committee.

Patent №: 12009430 (June 11, 2024) – Method for gate stack formation and etching. To improve profiles in vertical, narrow pitch, high aspect ratio features like FinFET gates, residue at the base of a substrate feature is minimized. A thin bottom layer of a different material, such as silicon germanium, is used. This material preferentially etches or oxidizes compared to the main layer, ensuring no un-etched residue remains. If residue does remain, it can be oxidized using plasma oxidation and then removed with standard oxide removal techniques.