Centurion+ Patent Holders as of August 27, 2024

Welcome to the 27th of August 2024: Our goal is to celebrate the patent holders who have reached noteworthy milestones in their fields this week.

Patent №: 12074204 (August 27, 2024) – Semiconductor structure and method for forming the same. Forming a semiconductor structure involves creating a fin with alternating semiconductor layers on a substrate, etching it to form a recess, and inserting a sacrificial contact. The first semiconductor layers are removed to create nanostructures after forming a source/drain feature and gate stack. The substrate is then removed, exposing the protective layer, and the sacrificial contact is replaced with a contact plug.

Patent №: 12074164 (August 27, 2024) – FinFET pitch scaling. Fabricating a semiconductor structure includes forming fin structures on a substrate, filling spaces with a sacrificial material, and creating a dummy gate with sidewall structures. The sacrificial material is laterally etched and replaced with a lower sidewall structure. After removing the dummy gate and sacrificial material, a real gate is formed over the fin structures.

A user device requesting an access and mobility (AM) policy decision from a second device and creating the SM policy based on the AM decision. It checks if the network devices are different using an identifier and sends a request to the second device if they are.

Patent №: 12074919 (August 27, 2024) – Systems and methods for reauthorization request notification. In some implementations, a network device receives a subscription request for notifications about context data for a user equipment (UE) session. The session has a reauthorization timer that triggers the device to request reauthorization. Upon the timer’s expiration, the network device sends the reauthorization request.

Patent №: 12072475 (August 27, 2024) – Miniature telephoto lens assembly.

An optical lens assembly with five aspheric lens elements has a TTL/EFL ratio of less than 1.0. The focal length of the first lens element is less than half of the TTL. The air gaps between the lens elements are set as follows: the gap between the first and second is less than half the thickness of the second lens, between the third and fourth is greater than TTL/5, and between the fourth and fifth is less than 1.5 times the thickness of the fifth lens.

The processor generates a Cryptographic Algorithm Identity (CAI) key pair and issues a CAI Certificate Signing Request (CSR) to a factory. It receives and stores a signed CAI certificate, which activates specific regional cryptographic algorithms stored in the firmware during manufacturing.

It measures signal and noise characteristics of memory cells to calculate an optimized read voltage. Using these characteristics, along with the bit error rate, it determines the amount of charge loss in the cells. The system tracks changes in the optimized read voltages based on this charge loss.

Patent №: 12073891 (August 27, 2024) – Integrated command to calibrate read voltage level. Processing logic in a memory device executes read operations at specific voltage levels and determines memory bit counts for each bin. It identifies the bin with the lowest bit count (valley center bin) and, if a condition is met, adjusts the read voltage level for that bin.