The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 30, 2006

Filed:

May. 15, 2002
Applicants:

Atsushi Okuno, Osaka-fu, JP;

Koichiro Nagai, Osaka-fu, JP;

Noriko Fujita, Osaka-fu, JP;

Yuki Ishikawa, Kyoto-fu, JP;

Noritaka Oyama, Osaka-fu, JP;

Tsunekazu Hashimoto, Shiga-ken, JP;

Inventors:

Atsushi Okuno, Osaka-fu, JP;

Koichiro Nagai, Osaka-fu, JP;

Noriko Fujita, Osaka-fu, JP;

Yuki Ishikawa, Kyoto-fu, JP;

Noritaka Oyama, Osaka-fu, JP;

Tsunekazu Hashimoto, Shiga-ken, JP;

Assignees:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/56 (2005.12); H01L 21/60 (2005.12);
U.S. Cl.
CPC ...
Abstract

The invention provides a method for producing semiconductor packages comprising the steps of forming electronic circuits for a plurality of semiconductor chipson a waferforming bumpson the plurality of semiconductor chipsencapsulating the circuit-forming surfaceof the waferand the bumpswith a sealant by screen printing means to form a sealant layercuring the sealant layergrinding the surface of the sealant layeruntil the upper end surface of the bumpbecomes exposed, placing solder balls on said upper end surface of bumpsto weld the balls to the surface thereof, and dicing the waferand the sealant layeras united into individual semiconductor chipsScreen printing means is used to encapsulate the entire surface of the wafer with a resin, so that the equipment costs can be markedly reduced as compared with conventional methods using a mold.


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