The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 12, 2018

Filed:

Apr. 13, 2017
Applicant:

Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu, TW;

Inventors:

Hsin-Hsiang Tseng, Changhua County, TW;

Jheng-Hong Jiang, Hsinchu, TW;

Fu-Cheng Chang, Tainan, TW;

Ching-Hung Kao, Tainan, TW;

Hsin-Chi Chen, Tainan, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/78 (2006.01); H01L 21/82 (2006.01); H01L 29/49 (2006.01); H01L 29/10 (2006.01); H01L 21/8238 (2006.01); H01L 29/66 (2006.01); H01L 27/092 (2006.01);
U.S. Cl.
CPC ...
H01L 29/7833 (2013.01); H01L 21/823814 (2013.01); H01L 21/823842 (2013.01); H01L 27/092 (2013.01); H01L 29/1033 (2013.01); H01L 29/4916 (2013.01); H01L 29/66492 (2013.01);
Abstract

The present disclosure provides a semiconductor device and a method of fabricating the semiconductor device. In some embodiments, the semiconductor device includes a substrate having a well region, a first source/drain region, a second source/drain region, a buried channel and a gate structure. The first source/drain region is located within the well region. The gate structure includes a co-doped gate including polysilicon and having a first concentration of a n-type impurity and a second concentration of a p-type impurity, in which the n-type impurity and the p-type impurity are mixed and distributed.


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