The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 12, 2018

Filed:

Dec. 22, 2014
Applicant:

Wensheng Qian, Shanghai, CN;

Inventor:

Wensheng Qian, Shanghai, CN;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 29/417 (2006.01); H01L 29/66 (2006.01); H01L 29/78 (2006.01); H01L 29/08 (2006.01);
U.S. Cl.
CPC ...
H01L 29/41783 (2013.01); H01L 29/0847 (2013.01); H01L 29/66659 (2013.01); H01L 29/7835 (2013.01);
Abstract

The present invention discloses an LDMOS device, whose drift region is composed of a first drift region and a second drift region, the first drift region being composed of an ion implantation region formed in a selected region of the silicon substrate; the second drift region, composed of the doped polysilicon formed on the surface of the silicon substrate, is superimposed on the first drift region, with the drain region formed in the second drift region. With the second drift region of the present invention, the thickness of the entire drift region can be increased, and thus the parasitic resistance of the entire drift region can be reduced, the linear current of the device can be effectively increased, and the on-resistance of the device can be effectively reduced; the device of the present invention can also maintain a high breakdown voltage and lower process cost. The present invention further discloses a method for manufacturing the LDMOS device.


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