The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 12, 2018
Filed:
Oct. 31, 2017
Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu, TW;
Chien-Kuo Su, Luzhu Township, TW;
Cheng Hung Lee, Hsinchu, TW;
Chiting Cheng, Taichung, TW;
Hung-Jen Liao, Hsinchu, TW;
Jonathan Tsung-Yung Chang, Hsinchu, TW;
Yen-Huei Chen, Jhudong Township, TW;
Pankaj Aggarwal, Zhudong Township, TW;
Jhon Jhy Liaw, Zhudong Township, TW;
TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsinchu, TW;
Abstract
A memory macro includes a first set of memory cells, a second set of memory cells, a third set of memory cells, a set of retention circuits and a set of conductive lines. The second set of memory cells arranged in a first row arranged in a second direction. The third set of memory cells arranged in a first column arranged in a first direction. The set of retention circuits is configured to supply a second voltage value of a second supply voltage to the first set of memory cells during a sleep operational mode. The set of retention circuits is responsive to a set of control signals, and arranged in a second column arranged in the first direction. The set of conductive lines extend in the second direction, and coupled to the set of retention circuits and the voltage supply node of the first set of memory cells.