The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 05, 2018
Filed:
Oct. 21, 2016
Applicant:
Stmicroelectronics, Inc., Coppell, TX (US);
Inventors:
Nicolas Loubet, Guiderland, NY (US);
Prasanna Khare, Schenectady, NY (US);
Assignee:
STMicroelectronics, Inc., Coppell, TX (US);
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/417 (2006.01); H01L 29/66 (2006.01); H01L 29/78 (2006.01); H01L 29/08 (2006.01); H01L 29/165 (2006.01); H01L 27/088 (2006.01); H01L 29/49 (2006.01);
U.S. Cl.
CPC ...
H01L 29/41791 (2013.01); H01L 27/0886 (2013.01); H01L 29/0847 (2013.01); H01L 29/165 (2013.01); H01L 29/4916 (2013.01); H01L 29/66545 (2013.01); H01L 29/66553 (2013.01); H01L 29/66795 (2013.01); H01L 29/785 (2013.01); H01L 29/7848 (2013.01); H01L 29/7851 (2013.01);
Abstract
A method of making a semiconductor device includes forming a fin mask layer on a semiconductor layer, forming a dummy gate over the fin mask layer, and forming source and drain regions on opposite sides of the dummy gate. The dummy gate is removed and the underlying fin mask layer is used to define a plurality of fins in the semiconductor layer. A gate is formed over the plurality of fins.