The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 05, 2018

Filed:

Dec. 21, 2016
Applicant:

Mediatek Inc., Hsin-Chu, TW;

Inventors:

Hsing-Chih Liu, Taichung, TW;

Chia-Hao Yang, Zhubei, TW;

Ying-Chih Chen, Kaohsiung, TW;

Assignee:

MediaTek Inc., Hsin-Chu, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/48 (2006.01); H01L 25/065 (2006.01); H01L 23/00 (2006.01);
U.S. Cl.
CPC ...
H01L 25/0655 (2013.01); H01L 24/09 (2013.01); H01L 24/49 (2013.01); H01L 2224/04042 (2013.01); H01L 2224/0603 (2013.01); H01L 2224/0612 (2013.01); H01L 2224/48139 (2013.01); H01L 2224/4912 (2013.01);
Abstract

A semiconductor package structure includes a base. A first die is mounted on the base. The first die includes a plurality of first pads arranged in a first tier, and a plurality of second pads arranged in a second tier. A second die is mounted on the base and includes a plurality of third pads with the first pad area, and a plurality of fourth pads with the second pad area, alternately arranged in a third tier. The second die also includes a first bonding wire having two terminals respectively coupled to one of the first pads and one of the fourth pads. The semiconductor package structure also includes a second bonding wire having two terminals respectively coupled to one of the third pads and one of the second pads.


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