The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 05, 2018

Filed:

Apr. 13, 2015
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Mantu K. Hudait, Blacksburg, VA (US);

Jack T. Kavalieros, Portland, OR (US);

Suman Datta, Beaverton, OR (US);

Marko Radosavljevic, Beaverton, OR (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/8238 (2006.01); B82Y 10/00 (2011.01); H01L 21/8252 (2006.01); H01L 21/8258 (2006.01); H01L 27/06 (2006.01); H01L 29/04 (2006.01); H01L 29/06 (2006.01); H01L 29/15 (2006.01); H01L 29/201 (2006.01); H01L 29/207 (2006.01); H01L 29/36 (2006.01); H01L 21/02 (2006.01);
U.S. Cl.
CPC ...
H01L 21/823807 (2013.01); B82Y 10/00 (2013.01); H01L 21/8252 (2013.01); H01L 21/8258 (2013.01); H01L 27/0605 (2013.01); H01L 29/045 (2013.01); H01L 29/0665 (2013.01); H01L 29/0673 (2013.01); H01L 29/151 (2013.01); H01L 29/201 (2013.01); H01L 29/207 (2013.01); H01L 29/365 (2013.01); H01L 21/02381 (2013.01); H01L 21/02463 (2013.01); H01L 21/02546 (2013.01);
Abstract

In one embodiment, the present invention includes a method for forming a logic device, including forming an n-type semiconductor device over a silicon (Si) substrate that includes an indium gallium arsenide (InGaAs)-based stack including a first buffer layer, a second buffer layer formed over the first buffer layer, a first device layer formed over the second buffer layer. Further, the method may include forming a p-type semiconductor device over the Si substrate from the InGaAs-based stack and forming an isolation between the n-type semiconductor device and the p-type semiconductor device. Other embodiments are described and claimed.


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