The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 05, 2018

Filed:

Sep. 28, 2016
Applicant:

Micro Materials Inc., Camarillo, CA (US);

Inventor:

Hao Tang, Chino Hills, CA (US);

Assignee:

Micro Materials Inc., Camarillo, CA (US);

Attorneys:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
B32B 38/10 (2006.01); H01L 21/683 (2006.01); B05D 1/00 (2006.01); B05D 1/32 (2006.01); C23C 14/22 (2006.01); B24B 37/20 (2012.01); C25D 7/12 (2006.01); C25D 17/06 (2006.01); H01L 21/67 (2006.01); B32B 43/00 (2006.01); B32B 37/06 (2006.01); B32B 37/12 (2006.01);
U.S. Cl.
CPC ...
H01L 21/6835 (2013.01); B05D 1/005 (2013.01); B05D 1/32 (2013.01); B24B 37/20 (2013.01); C23C 14/22 (2013.01); C25D 7/12 (2013.01); C25D 17/06 (2013.01); H01L 21/67092 (2013.01); B32B 37/06 (2013.01); B32B 37/12 (2013.01); B32B 38/10 (2013.01); B32B 43/006 (2013.01); B32B 2307/20 (2013.01); B32B 2457/14 (2013.01); H01L 21/6836 (2013.01); H01L 2221/6834 (2013.01); H01L 2221/68318 (2013.01); H01L 2221/68327 (2013.01); H01L 2221/68381 (2013.01); Y10T 156/1111 (2015.01); Y10T 156/1116 (2015.01); Y10T 156/1137 (2015.01); Y10T 156/1153 (2015.01); Y10T 156/1158 (2015.01); Y10T 156/1184 (2015.01); Y10T 156/1911 (2015.01); Y10T 156/1917 (2015.01); Y10T 156/1939 (2015.01); Y10T 156/1967 (2015.01);
Abstract

The present invention provides a procedure of processing a workpiece such as backside grinding of a device wafer and an apparatus designed for the procedure. The procedure comprises (1) preparing a bonded stack comprising (e.g. consisting of) a carrier layer, a workpiece layer, and an interposer layer therebetween; (2) processing the workpiece layer; and (3) delivering a gas jet at the junction between two adjacent layers in the stack to separate or debond the two adjacent layers. Technical merits of the invention include enhanced efficiency, higher wafer throughput, reduced stress on workpiece surface, and uniformly distributed stress and avoidance of device wafer breakage and internal device damage, among others.


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