The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 29, 2018

Filed:

Oct. 24, 2016
Applicant:

Taiwan Semiconductor Manufacturing Co., Ltd., Hsin-Chu, TW;

Inventors:

Shiu-Ko Jangjian, Tainan, TW;

Chi-Cherng Jeng, Tainan, TW;

Chih-Nan Wu, Tainan, TW;

Chun-Che Lin, Tainan, TW;

Ting-Chun Wang, Tainan, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/00 (2006.01); H01L 29/00 (2006.01); H01L 29/78 (2006.01); H01L 29/06 (2006.01); H01L 29/66 (2006.01); H01L 21/02 (2006.01); H01L 29/161 (2006.01); H01L 29/20 (2006.01);
U.S. Cl.
CPC ...
H01L 29/7851 (2013.01); H01L 21/0228 (2013.01); H01L 21/02274 (2013.01); H01L 29/0649 (2013.01); H01L 29/161 (2013.01); H01L 29/20 (2013.01); H01L 29/66545 (2013.01); H01L 29/66795 (2013.01); H01L 29/785 (2013.01); H01L 29/7848 (2013.01);
Abstract

A fin field device structure and method for forming the same are provided. The FinFET device structure includes a substrate and a fin structure extending from the substrate. The FinFET device structure also includes an isolation structure formed on the substrate. The fin structure has a top portion and a bottom portion, and the bottom portion is embedded in the isolation structure. The FinFET device structure further includes a protection layer formed on the top portion of the fin structure. An interface is between the protection layer and the top portion of the fin structure, and the interface has a roughness in a range from about 0.1 nm to about 2.0 nm.


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