The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 29, 2018

Filed:

Jun. 30, 2016
Applicant:

International Business Machines Corporation, Armonk, NY (US);

Inventors:

Kangguo Cheng, Schenectady, NY (US);

James J. Demarest, Rensselaer, NY (US);

John G. Gaudiello, Waterford, NY (US);

Juntao Li, Cohoes, NY (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/06 (2006.01); H01L 29/161 (2006.01); H01L 27/06 (2006.01); H01L 21/8234 (2006.01); H01L 21/311 (2006.01); H01L 21/02 (2006.01); H01L 29/66 (2006.01);
U.S. Cl.
CPC ...
H01L 29/0665 (2013.01); H01L 21/02175 (2013.01); H01L 21/02532 (2013.01); H01L 21/31111 (2013.01); H01L 21/823412 (2013.01); H01L 21/823481 (2013.01); H01L 27/0629 (2013.01); H01L 29/161 (2013.01); H01L 29/66545 (2013.01);
Abstract

A semiconductor device and process of making the same generally includes simultaneously forming nanosheet capacitors with nanosheet FET devices on the same substrate. The nanosheets in the capacitor have a width and are coupled to one another by sacrificial layers, wherein the sacrificial layers have a width smaller than the nanosheet width, and wherein the nanosheets and the sacrificial layers are conductively coupled to the substrate. The nanosheets in the FET devices are spaced apart and free of sacrificial layers. The nanosheets in the FET device have a width less than half the width of the nanosheets in the capacitor region.


Find Patent Forward Citations

Loading…