The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 29, 2018

Filed:

Oct. 15, 2015
Applicant:

Taiwan Semiconductor Manufacturing Co., Ltd., Hsin-Chu, TW;

Inventors:

Wei Cheng Wu, Zhubei, TW;

Jui-Tsung Lien, Hsinchu, TW;

Fang-Lan Chu, Taichung, TW;

Hong-Da Lin, Taipei, TW;

Ku-Ning Chang, Taichung, TW;

Yu-Chen Wang, Huwei Township, TW;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 21/768 (2006.01); G01R 31/26 (2014.01); H01L 23/544 (2006.01); H01L 23/528 (2006.01); H01L 29/51 (2006.01); H01L 29/49 (2006.01); H01L 27/11568 (2017.01); H01L 29/423 (2006.01); H01L 21/3213 (2006.01); H01L 27/11573 (2017.01); H01L 21/66 (2006.01);
U.S. Cl.
CPC ...
G01R 31/2644 (2013.01); H01L 21/32133 (2013.01); H01L 21/76877 (2013.01); H01L 23/528 (2013.01); H01L 23/544 (2013.01); H01L 27/11568 (2013.01); H01L 27/11573 (2013.01); H01L 29/42344 (2013.01); H01L 29/4916 (2013.01); H01L 29/513 (2013.01); H01L 22/34 (2013.01); H01L 2223/5446 (2013.01); H01L 2223/54406 (2013.01); H01L 2223/54453 (2013.01);
Abstract

The present disclosure relates to a substrate having test line letters that are used to identify a test line on an integrated chip, while avoiding contamination of high-k metal gate processes, and a method of formation. In some embodiments, an integrated chip is disclosed. The integrated chip has a semiconductor substrate. A test line letter is arranged over the semiconductor substrate. The test line letter comprises a positive relief that protrudes outward from the semiconductor substrate in the shape of an alpha-numeric character. One or more dummy structures are arranged over the semiconductor substrate. The one or more dummy structures are proximate to a boundary of the test line letter.


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