The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 22, 2018

Filed:

Mar. 18, 2016
Applicant:

Taiwan Semiconductor Manufacturing Co., Ltd., Hsin-Chu, TW;

Inventors:

Chien-Yuan Chen, Hsinchu, TW;

Cheng Hung Lee, Hsinchu, TW;

Hung-Jen Liao, Hsin-Chu, TW;

Hau-Tai Shieh, Hsinchu, TW;

Che-Ju Yeh, Hsin-Chu, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03L 5/00 (2006.01); H03K 19/0185 (2006.01);
U.S. Cl.
CPC ...
H03K 19/018521 (2013.01);
Abstract

A circuit is disclosed. The circuit includes eight MOD transistors and a capacitor, the first MOS transistor having a source coupled to a first predetermined supply voltage (VDDM), a second MOS transistor having a source coupled to a first predetermined supply voltage VDDM, a third MOS transistor having a source coupled to a drain of the first MOS transistor, a fourth MOS transistor having a source coupled to a drain of the second MOS transistor, a fifth MOS transistor having a source coupled to a drain of the third MOS transistor and a gate of the second MOS transistor, and a gate coupled to a gate of the third MOS transistor and an input node, and a drain coupled to ground, a sixth MOS transistor having a source coupled to a drain of the fourth MOS transistor and a gate of the first MOS transistor and an output node.


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