The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 15, 2018

Filed:

Sep. 02, 2016
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Keith D. Underwood, Albuquerque, NM (US);

Steffen Kosinski, Braunschweig, DE;

Jaroslaw Topp, Schoeppenstedt, DE;

Jan Norden, Braunschweig, DE;

Michael Redeker, Braunschweig, DE;

Assignee:

INTEL CORPORATION, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H04L 29/04 (2006.01); H04L 12/721 (2013.01); G06F 15/167 (2006.01); G06F 13/38 (2006.01); H04L 12/773 (2013.01); H04L 1/12 (2006.01); H04L 12/26 (2006.01); H04L 12/801 (2013.01); H04L 29/08 (2006.01); H04L 1/18 (2006.01);
U.S. Cl.
CPC ...
H04L 45/38 (2013.01); G06F 13/385 (2013.01); G06F 15/167 (2013.01); H04L 1/12 (2013.01); H04L 45/60 (2013.01); H04L 1/1835 (2013.01); H04L 43/103 (2013.01); H04L 47/34 (2013.01); H04L 67/10 (2013.01); Y02B 60/1228 (2013.01); Y02B 60/1235 (2013.01);
Abstract

Methods related to communication between and within nodes in a high performance computing system are presented. Processing time for message exchange between a processing unit and a network controller interface in a node is reduced. Resources required to manage application state in the network interface controller are minimized. In the network interface controller, multiple contexts are multiplexed into one physical Direct Memory Access engine. Virtual to physical address translation in the network interface controller is accelerated by using a plurality of independent caches, with each level of the page table hierarchy cached in an independent cache. A memory management scheme for data structures distributed between the processing unit and the network controller interface is provided. The state required to implement end-to-end reliability is reduced by limiting the transmit sequence number space to the currently in-flight messages.


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