The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 15, 2018

Filed:

Mar. 27, 2016
Applicant:

United Microelectronics Corp., Hsin-Chu, TW;

Inventors:

Fu-Shou Tsai, Keelung, TW;

Yu-Ting Li, Chiayi, TW;

Chih-Hsun Lin, Ping-Tung County, TW;

Li-Chieh Hsu, Taichung, TW;

Yi-Liang Liu, Tainan, TW;

Po-Cheng Huang, Kaohsiung, TW;

Kun-Ju Li, Tainan, TW;

Wen-Chin Lin, Tainan, TW;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
B23P 15/00 (2006.01); C03C 25/00 (2018.01); C23F 1/00 (2006.01); B44C 1/22 (2006.01); C03C 15/00 (2006.01); C03C 25/68 (2006.01); H01L 21/28 (2006.01); H01L 29/66 (2006.01); H01L 21/02 (2006.01); H01L 21/3105 (2006.01);
U.S. Cl.
CPC ...
H01L 21/28247 (2013.01); H01L 21/0223 (2013.01); H01L 21/02247 (2013.01); H01L 21/31056 (2013.01); H01L 29/66545 (2013.01);
Abstract

A method of fabricating a gate cap layer includes providing a substrate with an interlayer dielectric disposed thereon, wherein a recess is disposed in the interlayer dielectric and a metal gate fills in a lower portion of the recess. Later, a cap material layer is formed to cover the interlayer dielectric and fill in an upper portion of the recess. After that, a first sacrifice layer and a second sacrifice layer are formed in sequence to cover the cap material layer. The first sacrifice layer has a composition different from a composition of the cap material layer. The second sacrifice layer has a composition the same as the composition of the cap material layer. Next, a chemical mechanical polishing process is preformed to remove the second sacrifice layer, the first sacrifice layer and the cap material layer above a top surface of the interlayer dielectric.


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