The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 08, 2018

Filed:

Dec. 14, 2012
Applicant:

Cypress Semiconductor Corporation, San Jose, CA (US);

Inventors:

Chun Chen, San Jose, CA (US);

Shenqing Fang, Fremont, CA (US);

Unsoon Kim, San Jose, CA (US);

Mark T. Ramsbey, Sunnyvale, CA (US);

Kuo Tung Chang, Saratoga, CA (US);

Sameer S. Haddad, San Jose, CA (US);

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 29/792 (2006.01); H01L 27/11573 (2017.01); H01L 29/423 (2006.01); H01L 29/66 (2006.01);
U.S. Cl.
CPC ...
H01L 29/792 (2013.01); H01L 27/11573 (2013.01); H01L 29/42344 (2013.01); H01L 29/66833 (2013.01);
Abstract

Embodiments provide a split gate device, methods for fabricating a split gate device, and integrated methods for fabricating a split gate device and a periphery device. In an embodiment, the split gate device is a charge trapping split gate device, which includes a charge trapping layer. In another embodiment, the split gate device is a non-volatile memory cell, which can be formed according to embodiments as standalone or embedded with a periphery device.


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