The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 08, 2018

Filed:

May. 13, 2016
Applicant:

Taiwan Semiconductor Manufacturing Co., Ltd., Hsin-Chu, TW;

Inventors:

Shyh-Wei Cheng, Zhudong Township, TW;

Hung-Lin Chen, Pingtung, TW;

Jui-Chun Weng, Taipei, TW;

Shiuan-Jeng Lin, Hsinchu, TW;

Tian Sheng Lin, Yangmei Township, TW;

Yu-Jui Wu, Hsin-Chu, TW;

Albion Pan, Hsin-Chu, TW;

Bob Sun, Hsin-Chu, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 49/02 (2006.01); H01L 23/522 (2006.01); H01L 21/3213 (2006.01); H01L 21/311 (2006.01);
U.S. Cl.
CPC ...
H01L 28/75 (2013.01); H01L 21/31111 (2013.01); H01L 21/32139 (2013.01); H01L 23/5223 (2013.01);
Abstract

A method for manufacturing a metal-insulator-metal (MIM) capacitor with a top electrode that is free of sidewall damage is provided. A bottom electrode layer is formed with a first material. An inter-electrode dielectric layer is formed over the bottom electrode layer. A top electrode layer is formed over the inter-electrode dielectric layer and without the first material. A first etch is performed into the top electrode layer and the inter-electrode dielectric layer to form a top electrode. A second etch into the bottom electrode layer to form a bottom electrode. The present application is also directed towards a MIM capacitor resulting from performing the method.


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