The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 08, 2018

Filed:

Jun. 26, 2017
Applicant:

Globalfoundries Inc., Grand Cayman, KY;

Inventors:

Haifeng Sheng, Rexford, NY (US);

Haigou Huang, Rexford, NY (US);

Tai Fong Chao, Clifton Park, NY (US);

Jiehui Shu, Clifton Park, NY (US);

Jinping Liu, Ballston Lake, NY (US);

Xingzhao Shi, Clifton Park, NY (US);

Laertis Economikos, Wappingers Falls, NY (US);

Assignee:

GLOBALFOUNDRIES INC., Grand Cayman, KY;

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/00 (2006.01); H01L 21/3105 (2006.01);
U.S. Cl.
CPC ...
H01L 21/31056 (2013.01);
Abstract

The disclosure is directed to methods of planarizing an integrated circuit structure including: forming a dielectric over a first nitride layer; planarizing the dielectric to a top surface of a set of nitride fins in a first region and removing the dielectric from a second region to expose the substantially planar upper surface in a second region; forming a second nitride layer over the dielectric and the top surface of the set of nitride fins and over the substantially planar upper surface; planarizing the second nitride layer such that the second nitride layer in the second region is planar with the top surface of the dielectric and the set of nitride fins, and such that the second nitride layer is removed from the first region; and performing an etch such that the first nitride layer in the first region is planar with the first nitride layer in the second region.


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