The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 01, 2018

Filed:

Jan. 12, 2016
Applicant:

International Business Machines Corporation, Armonk, NY (US);

Inventors:

Ruqiang Bao, Niskayuna, NY (US);

Keith Kwong Hon Wong, Wappingers Falls, NY (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 29/772 (2006.01); H01L 21/28 (2006.01); H01L 29/78 (2006.01); H01L 21/425 (2006.01); H01L 27/092 (2006.01); H01L 29/40 (2006.01); H01L 29/51 (2006.01); H01L 29/49 (2006.01); H01L 21/8238 (2006.01); H01L 21/768 (2006.01); H01L 29/161 (2006.01);
U.S. Cl.
CPC ...
H01L 27/092 (2013.01); H01L 21/28088 (2013.01); H01L 21/28255 (2013.01); H01L 21/76843 (2013.01); H01L 21/823842 (2013.01); H01L 21/823857 (2013.01); H01L 29/161 (2013.01); H01L 29/4958 (2013.01); H01L 29/4966 (2013.01); H01L 29/517 (2013.01); H01L 29/518 (2013.01);
Abstract

In one embodiment, a method of making a semiconductor device includes: forming a substrate; forming an nFET transistor and a pFET transistor on the substrate; wherein forming the nFET transistor comprises first depositing several first layers in and along the inner sidewalls of a trench on the substrate, then depositing a conductive metal comprising cobalt on the several first layers; wherein forming the pFET transistor comprises first depositing several second layers in and along the inner sidewalls of a trench on the substrate, then depositing a conductive metal comprising cobalt on the several second layers.


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