The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 01, 2018

Filed:

Apr. 13, 2017
Applicant:

United Microelectronics Corp., Hsin-Chu, TW;

Inventors:

Ying-Chiao Wang, Changhua County, TW;

Yu-Hsiang Hung, Tainan, TW;

Chao-Hung Lin, Changhua County, TW;

Ssu-I Fu, Kaohsiung, TW;

Chih-Kai Hsu, Tainan, TW;

Jyh-Shyang Jenq, Pingtung County, TW;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/544 (2006.01); H01L 21/28 (2006.01); H01L 21/033 (2006.01); H01L 21/311 (2006.01);
U.S. Cl.
CPC ...
H01L 23/544 (2013.01); H01L 21/0337 (2013.01); H01L 21/28008 (2013.01); H01L 21/31144 (2013.01); H01L 2223/5442 (2013.01); H01L 2223/5446 (2013.01); H01L 2223/54426 (2013.01);
Abstract

The present invention provides a method of forming a semiconductor structure. A wafer with a dicing region is provided, the dicing region comprises a central region, a middle region surrounds the central region, and a peripheral region surrounds the middle region. Next, an aligning mark is formed in the dicing region, wherein the aligning mark is a mirror symmetrical pattern and comprises a plurality of second patterns in the middle region and a plurality of third patterns in the third region, each third pattern has a plurality of lines and the lines comprises a plurality of inner lines which are formed by a sidewall image transfer (SIT) process.


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