The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 24, 2018
Filed:
Mar. 24, 2016
Taiwan Semiconductor Manufacturing Company, Ltd., Hsin-Chu, TW;
Ming-Chyi Liu, Hsin-Chu, TW;
Pei-Lun Wang, Zhubei, TW;
Yuan-Tai Tseng, Zhubei, TW;
Yu-Hsing Chang, Taipei, TW;
Shih-Chang Liu, Alian Township, TW;
Taiwan Semiconductor Manufacturing Company, Ltd., Hsin-Chu, TW;
Abstract
A method includes forming a gate spacer along sidewalls of a gate structure, forming a source region and a drain region on opposite sides of the gate structure, wherein a sidewall of the source region is vertically aligned with a first sidewall of the gate spacer, depositing a dielectric layer over the substrate, depositing a conductive layer over the dielectric layer, patterning the dielectric layer and the conductive layer to form a field plate, wherein the dielectric layer comprises a horizontal portion extending from the second drain/source region to a second sidewall of the gate spacer and a vertical portion formed along the second sidewall of the gate spacer, forming a plurality of metal silicide layers by applying a salicide process to the conductive layer, the gate structure, the first drain/source region and the second drain/source region and forming contact plugs over the plurality of metal silicide layers.