The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 24, 2018

Filed:

Feb. 03, 2017
Applicant:

Taiwan Semiconductor Manufacturing Co., Ltd., Hsin-Chu, TW;

Inventors:

Hsueh-Liang Chou, Jhubei, TW;

Dah-Chuen Ho, Zhubei, TW;

Hui-Ting Lu, Zhudong Township, TW;

Po-Chih Su, New Taipei, TW;

Pei-Lun Wang, Zhubei, TW;

Yu-Chang Jong, Hsinchu, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/40 (2006.01); H01L 29/78 (2006.01); H01L 29/66 (2006.01);
U.S. Cl.
CPC ...
H01L 29/7816 (2013.01); H01L 29/402 (2013.01); H01L 29/66681 (2013.01); H01L 29/7835 (2013.01);
Abstract

The present disclosure relates to a transistor device having a field plate, and a method of formation. In some embodiments, the transistor device has a gate electrode disposed over a substrate between a source region and a drain region. One or more dielectric layers laterally extend from over the gate electrode to a location between the gate electrode and the drain region. A field plate is located within an inter-level dielectric (ILD) layer overlying the substrate. The field plate laterally extends from over the gate electrode to over the location and vertically extends from the one or more dielectric layers to a top surface of the ILD layer. A conductive contact is arranged over the drain region and is surrounded by the ILD layer. The conductive contact extends to the top surface of the ILD layer.


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