The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 24, 2018

Filed:

Jun. 27, 2016
Applicant:

University of Notre Dame Du Lac, Notre Dame, IN (US);

Inventors:

Patrick Fay, Granger, IN (US);

Lina Cao, Notre Dame, IN (US);

Debdeep Jena, Ithaca, NY (US);

Wenjun Li, South Bend, IN (US);

Assignee:

University of Notre Dame due Lac, South Bend, IN (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/66 (2006.01); H01L 29/20 (2006.01); H01L 29/205 (2006.01); H01L 29/06 (2006.01); H01L 29/423 (2006.01); H01L 29/786 (2006.01);
U.S. Cl.
CPC ...
H01L 29/66977 (2013.01); H01L 29/0669 (2013.01); H01L 29/2003 (2013.01); H01L 29/205 (2013.01); H01L 29/42392 (2013.01); H01L 29/66522 (2013.01); H01L 29/66742 (2013.01); H01L 29/78618 (2013.01); H01L 29/78681 (2013.01); H01L 29/78696 (2013.01);
Abstract

A tunnel field-effect transistor device includes a p-type GaN source layer, an ntype GaN drain layer, and an interlayer interfaced between the source-layer and the drain layer. These devices employ polarization engineering in GaN/InN heterojunctions to achieve appreciable interband tunneling current densities. In one example, the interlayer includes an Indium Nitride (InN) layer. In one example, the interlayer includes a graded Indium gallium nitride layer and an InN layer. In one example, the interlayer may include a graded Indium gallium nitride (InGaN) layer and an Indium gallium nitride (InGaN) layer. In one example, the tunnel field-effect transistor device includes an in-line configuration. In one example, the tunnel field-effect transistor device includes a side-wall configuration. In one example, the tunnel field-effect transistor device includes a nanowire cylindrical gate-all-around geometry to achieve a high degree of gate electrostatic control.


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