The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 24, 2018
Filed:
Mar. 25, 2016
Applicant:
Force Mos Technology Co., Ltd., New Taipei, TW;
Inventor:
Fu-Yuan Hsieh, New Taipei, TW;
Assignee:
FORCE MOS TECHNOLOGY CO., LTD., New Taipei, TW;
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 29/66 (2006.01); H01L 27/02 (2006.01); H01L 29/40 (2006.01); H01L 29/78 (2006.01); H01L 23/535 (2006.01); H01L 23/532 (2006.01);
U.S. Cl.
CPC ...
H01L 27/0255 (2013.01); H01L 23/535 (2013.01); H01L 23/53266 (2013.01); H01L 29/407 (2013.01); H01L 29/66734 (2013.01); H01L 29/7805 (2013.01); H01L 29/7808 (2013.01); H01L 29/7813 (2013.01);
Abstract
A semiconductor power device having shielded gate structure in an active area and having ESD clamp diode with two poly-silicon layer process is disclosed, wherein: the shielded gate structure comprises a first poly-silicon layer to serve as a shielded electrode and a second poly-silicon layer to serve as a gate electrode, and the ESD clamp diode formed between two protruding electrodes is also formed by the first poly-silicon layer. A mask specially used to define the ESD clamp diode portion is saved.