The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 17, 2018

Filed:

Apr. 04, 2017
Applicant:

United Microelectronics Corp., Hsin-Chu, TW;

Inventors:

Ting-Chia Chang, Chiayi, TW;

Shih-Hao Liang, Tainan, TW;

Chun-Yen Tseng, Tainan, TW;

Yu-Tse Kuo, Tainan, TW;

Ching-Cheng Lung, Tainan, TW;

Hung-Chan Lin, Tainan, TW;

Shao-Hui Wu, Singapore, SG;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/02 (2006.01); H01L 27/11 (2006.01); G11C 11/412 (2006.01); H01L 29/24 (2006.01);
U.S. Cl.
CPC ...
H01L 27/1104 (2013.01); G11C 11/412 (2013.01); H01L 27/0207 (2013.01); H01L 27/1116 (2013.01); H01L 29/24 (2013.01);
Abstract

The present invention provides a semiconductor memory device, includes at least one static random access memory (SRAM) cell, wherein the SRAM cell includes a first pick-up node, and a dielectric oxide SRAM (DOSRAM), disposed in a first dielectric layer and disposed above the SRAM cell when viewed in a cross section view, wherein the DOSRAM includes an oxide semiconductor filed effect transistor (OSFET) and a capacitor, a source of the OSFET is electrically connected to the first pick-up node of the SRAM cell through a via structure, and at least parts of the first dielectric layer are disposed between the source of the OSFET and the via structure, and the capacitor is disposed above the OSFET and electrically connected to a drain of the OSFET when viewed in the cross section view.


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