The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 10, 2018

Filed:

Sep. 22, 2017
Applicant:

Etron Technology, Inc., Hsinchu, TW;

Inventors:

Weng-Dah Ken, Hsinchu, TW;

Chao-Chun Lu, Taipei, TW;

Jan-Mye Sung, Taoyuan, TW;

Assignee:

Etron Technology, Inc., Hsinchu, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 13/42 (2006.01); H01L 23/544 (2006.01); H01L 23/58 (2006.01); H01L 25/065 (2006.01); H01L 25/18 (2006.01); G11C 5/06 (2006.01); G11C 8/18 (2006.01); G06F 13/40 (2006.01);
U.S. Cl.
CPC ...
G06F 13/4234 (2013.01); G06F 13/4018 (2013.01); G06F 13/42 (2013.01); G11C 5/06 (2013.01); G11C 8/18 (2013.01); H01L 23/544 (2013.01); H01L 23/585 (2013.01); H01L 25/0652 (2013.01); H01L 25/0657 (2013.01); H01L 25/18 (2013.01); H01L 2223/5442 (2013.01); H01L 2223/54426 (2013.01); H01L 2223/54473 (2013.01); H01L 2224/16146 (2013.01); H01L 2224/16227 (2013.01); H01L 2224/17181 (2013.01); H01L 2224/48227 (2013.01); H01L 2225/0651 (2013.01); H01L 2225/06513 (2013.01); H01L 2225/06517 (2013.01); H01L 2225/06541 (2013.01); H01L 2924/15311 (2013.01); H01L 2924/3025 (2013.01); Y02B 60/1228 (2013.01); Y02B 60/1235 (2013.01);
Abstract

A reconfigurable high speed memory chip module includes a type of memory cell array group, a first transmission bus, and a logic unit. The type memory cell array group includes multiple memory cell array integrated circuits (ICs). The first transmission bus coupled to the type memory cell array group has a first programmable transmitting or receiving data rate, a first programmable transmitting or receiving signal swing, a first programmable bus width, and a combination thereof. The logic unit is coupled to the first transmission bus for accessing the type memory cell array group through the first transmission bus.


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