The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 03, 2018

Filed:

Feb. 29, 2016
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

James Mathew, Boise, ID (US);

Yunjun Ho, Boise, ID (US);

Zhiqiang Xie, Meridian, ID (US);

Hyun Sik Kim, Boise, ID (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/70 (2006.01); H01L 21/762 (2006.01); H01L 21/02 (2006.01); H01L 25/00 (2006.01); H01L 25/065 (2006.01); H01L 27/115 (2017.01); H01L 21/66 (2006.01);
U.S. Cl.
CPC ...
H01L 21/76232 (2013.01); H01L 21/02271 (2013.01); H01L 21/02282 (2013.01); H01L 22/26 (2013.01); H01L 25/0657 (2013.01); H01L 25/50 (2013.01); H01L 27/115 (2013.01);
Abstract

A disclosed example to modulate slit stress in a semiconductor substrate includes controlling a first process to apply a first material to a semiconductor substrate. The semiconductor substrate includes a slit between adjacent stacked transistor layers. The first material coats walls of the slit to reduce a first width of the slit between the adjacent stacked transistor layers to a second width. A second process is controlled to apply a second material to the semiconductor substrate. The second material is to be deposited in the second width of the slit. The first material and the second material are to form a solid structure in the slit between the adjacent stacked transistor layers.


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