The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 03, 2018

Filed:

Mar. 26, 2015
Applicant:

Freescale Semiconductor, Inc., Austin, TX (US);

Inventors:

Inder Mohan Bhawnani, Gwalior, IN;

Ertugrul Demircan, Eugene, OR (US);

Dwarka Prasad, Noida, IN;

Douglas M. Reber, Austin, TX (US);

Donald E. Smeltzer, Austin, TX (US);

Kenneth J. Danti, Austin, TX (US);

Assignee:

NXP USA, INC., Austin, TX (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 9/455 (2018.01); G06F 17/50 (2006.01);
U.S. Cl.
CPC ...
G06F 17/5081 (2013.01);
Abstract

A method for design rule verification is provided. The method comprises: providing a design rule check (DRC) deck based on a design rule manual (DRM) having a plurality of design rules; providing a plurality of primitive objects; creating a plurality of collection objects, each collection object using one or more primitive objects; using the plurality of collection objects, creating a plurality of DRM test cases; assigning names to each of the plurality of DRM test cases, each of the names based on a rule name of the plurality of design rules and on an expected pass or fail indication; and using the plurality of named DRM test cases to verify the DRC deck.


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