The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 27, 2018

Filed:

Jun. 07, 2013
Applicants:

Yan Xun Xue, Los Gatos, CA (US);

Yueh-se Ho, Sunnyvale, CA (US);

Hamza Yilmaz, Saratoga, CA (US);

Jun LU, San Jose, CA (US);

Inventors:

Yan Xun Xue, Los Gatos, CA (US);

Yueh-Se Ho, Sunnyvale, CA (US);

Hamza Yilmaz, Saratoga, CA (US);

Jun Lu, San Jose, CA (US);

Assignee:
Attorneys:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 23/495 (2006.01); H01L 23/48 (2006.01); H01L 23/52 (2006.01); H01L 23/00 (2006.01); H01L 23/492 (2006.01);
U.S. Cl.
CPC ...
H01L 23/4951 (2013.01); H01L 23/49541 (2013.01); H01L 23/49548 (2013.01); H01L 24/73 (2013.01); H01L 23/492 (2013.01); H01L 23/49513 (2013.01); H01L 23/49562 (2013.01); H01L 2224/16245 (2013.01); H01L 2224/48091 (2013.01); H01L 2224/49111 (2013.01); H01L 2224/92247 (2013.01); H01L 2924/01322 (2013.01); H01L 2924/13091 (2013.01);
Abstract

The invention relates to a semiconductor package of a flip chip and a method for making the semiconductor package. The semiconductor chip comprises a metal-oxide-semiconductor field effect transistor. On a die paddle including a first base, a second base and a third base, half-etching or punching is performed on the top surfaces of the first base and the second base to obtain plurality of grooves that divide the top surface of the first base into a plurality of areas comprising multiple first connecting areas, and divide the top surface of the second base into a plurality of areas comprising at least a second connecting area. The semiconductor chip is connected to the die paddle at the first connecting areas and the second connecting area.


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