The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 27, 2018
Filed:
Oct. 14, 2015
Taiwan Semiconductor Manufacturing Co., Ltd., Hsin-Chu, TW;
Yung-Yao Lee, Zhubei, TW;
Ying-Ying Wang, Xin-Zhu, TW;
Taiwan Semiconductor Manufacturing Co., Ltd., Hsin-Chu, TW;
Abstract
One embodiment relates to a method for overlay sampling. The method provides a number of fields over a semiconductor wafer surface. An inner subgroup of the number of fields includes fields in a central region of the wafer surface. An outer subgroup of the number of fields includes neighboring fields near a circumferential edge of the wafer surface. The method measures a first number of overlay conditions at a corresponding first number of overlay structures within a field of the inner subgroup. The method also measures a second number of overlay conditions at a corresponding second number of overlay structures within a field of the outer subgroup. The second number is greater than the first number. Based on the measured first number of overlay conditions and the measured second number of overlay conditions, the method determines an alignment condition for two or more layers on the semiconductor wafer surface.