The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 20, 2018
Filed:
Jun. 24, 2016
Mie Fujitsu Semiconductor Limited, Kuwana, Mie, JP;
Reza Arghavani, Scotts Valley, CA (US);
Pushkar Ranade, Los Gatos, CA (US);
Lucian Shifren, San Jose, CA (US);
Scott E. Thompson, Gainesville, FL (US);
Catherine de Villeneuve, San Jose, CA (US);
Mie Fujitsu Semiconductor Limited, Kuwana, JP;
Abstract
A structure and method of fabrication thereof relate to a Deeply Depleted Channel (DDC) design, allowing CMOS based devices to have a reduced σV(variation in V) compared to conventional bulk CMOS and can allow the threshold voltage Vof FETs having dopants in the channel region to be set much more precisely. A novel dopant profile indicative of a distinctive notch enables tuning of the Vsetting within a precise range. This Vset range may be extended by appropriate selection of metals of a gate electrode material so that a very wide range of Vsettings is accommodated on the die. The DDC design also can have a strong body effect compared to conventional bulk CMOS transistors, which can allow for significant dynamic control of power consumption in DDC transistors. The result is the ability to independently control V(with a low σV) and V(the operating voltage supplied to the transistor), so that the body bias can be tuned separately from Vfor a given device.